The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2017

Filed:

Jul. 24, 2014
Applicant:

Google Technology Holdings Llc, Mountain View, CA (US);

Inventors:

Scott P DeBates, Crystal Lake, IL (US);

George B Standish, Marengo, IL (US);

Nathan M Connell, Hawthorn Woods, IL (US);

Parikshit Dharawat, Sunnyvale, CA (US);

Christian L Flowers, Chicago, IL (US);

Jared S Suttles, Mundelein, IL (US);

Joseph H Swantek, Fox River Grove, IL (US);

Haitang Wang, San Jose, CA (US);

Assignee:

Google Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 13/00 (2006.01); G06F 1/32 (2006.01); G06F 9/54 (2006.01); G06F 3/0488 (2013.01);
U.S. Cl.
CPC ...
G06F 1/3293 (2013.01); G06F 1/3209 (2013.01); G06F 1/3287 (2013.01); G06F 1/3206 (2013.01); G06F 3/0488 (2013.01); G06F 9/542 (2013.01); Y02B 60/121 (2013.01);
Abstract

One disclosed method includes generating a rule set by an application running on a primary processor. The rule set specifies how the application handles events. The rule set is sent from the primary processor to a secondary processor and the primary processor is placed in sleep mode. The secondary processor may then handle at least one event corresponding to the application by executing the rule set while the primary processor is in sleep mode. In one embodiment, handling the event may include substituting for the application by the secondary processor by executing the rule set, and controlling a peripheral hardware device that is peripheral to the primary processor according to the rule set. Handling an event may also include waking the primary processor from sleep mode by the secondary processor and passing control back to the primary processor.


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