The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2017

Filed:

Jun. 13, 2016
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Beijing Boe Display Technology Co., Ltd., Beijing, CN;

Inventors:

Cong Liu, Beijing, CN;

Yuchun Feng, Beijing, CN;

Chunze Zhang, Beijing, CN;

Zhaohui Hao, Beijing, CN;

Lin Li, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1345 (2006.01); G02F 1/1368 (2006.01); G02F 1/1362 (2006.01); H01L 27/12 (2006.01); H01L 21/78 (2006.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
G02F 1/1368 (2013.01); G01R 31/2884 (2013.01); G02F 1/136227 (2013.01); G02F 1/136286 (2013.01); H01L 21/78 (2013.01); H01L 27/124 (2013.01); H01L 27/1255 (2013.01); H01L 27/1262 (2013.01); G02F 2001/136295 (2013.01);
Abstract

A method of manufacturing an array substrate includes: forming a first functional layer comprising a plurality of array substrate areas and connection areas between adjacent array substrate areas; forming a plurality of conductive portions within each of the array substrate areas, the plurality of conductive portions extending from a corresponding one of the array substrate areas to a corresponding one of the connection areas and terminals of the plurality of conductive portions being in connection with capacitor lines within the corresponding one of the connection areas such that two capacitor lines between two adjacent array substrate areas face each other and are formed into a first capacitor element; forming a plurality of second functional layers on the first functional layer formed with the plurality of conductive portions and the capacitor lines, for forming a plurality of array substrates; and performing a cutting process at the connection areas between adjacent array substrates and removing the capacitor lines between the adjacent array substrates so as to form a plurality of separate array substrates. The present disclosure further provides an array substrate manufactured by the method.


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