Clock phase alignment in data transmission

Abstract

A system and method are described for calibrating a clock used in data transmission. In one example, dynamic phase adjustment circuitry can be used for any of a variety of different protocols to shift the clock phase with respect to a data signal. In the most typical example, the clock phase is shifted 90 degrees relative to a transmission data signal. The dynamic phase adjustment circuitry can use two cascaded programmable delay lines coupled in series. Each programmable delay line represents a half phase delay of 90 degrees. A controller can monitor an output of the programmable delay lines and incrementally add or subtract programmable delay line elements until a 180 degree phase is detected relative to a data transmission. An output clock can then be used by applying the result of the calibration delay element to the clock under discussion.