The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2017

Filed:

Jan. 18, 2017
Applicant:

Novatek Microelectronics Corp., Hsinchu, TW;

Inventors:

Shih-Chun Lin, Kaohsiung, TW;

Ren-Hong Luo, Hsinchu, TW;

Mu-Jung Chen, Tainan, TW;

Yung-Cheng Lin, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 9/00 (2006.01); H03K 5/01 (2006.01); H03K 3/037 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03M 9/00 (2013.01); H03K 3/037 (2013.01); H03K 5/01 (2013.01); H03K 2005/00019 (2013.01);
Abstract

The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.


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