Clock circuit and clock signal transmission method thereof

Abstract

A clock circuit includes a buffer module, N multiplexers, and N clock gating cells. The buffer module includes an input end and N output ends, and is configured to enhance a driving capability of a clock signal received by the input end, and output the clock signal from the N output ends, and the N output ends are connected to data ends of the N clock gating cells one to one. Output ends of the N first multiplexers are connected to enabling ends of the N clock gating cells one to one. Each clock gating cell outputs a clock signal from an output end according to a frequency division logic signal or a gating logic signal received by an enabling end from an output end of a corresponding multiplexer and the clock signal received by a data end from an output end of the buffer module.