The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2017

Filed:

Apr. 29, 2016
Applicant:

Avago Technologies General Ip (Singapore) Pte. Ltd., Singapore, SG;

Inventors:

Dechang Sun, Eden Prairie, MN (US);

Wei Zhang, Eagan, MN (US);

Mai T. MacLennan, Plymouth, MN (US);

Sudeep Ashok Pomar, Chanhassen, MN (US);

Roy M. Carlson, Hamel, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 17/14 (2006.01); G11C 17/08 (2006.01); G11C 14/00 (2006.01); G11C 17/10 (2006.01);
U.S. Cl.
CPC ...
G11C 17/14 (2013.01); G11C 14/00 (2013.01); G11C 17/08 (2013.01); G11C 17/10 (2013.01);
Abstract

Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory array includes a plurality of memory cells to store data bits. Each of the plurality of memory cells includes a transistor having drain, source, and gate terminals, and a plurality of program nodes, each of the program nodes charged to a predetermined voltage and coupled to a respective one of a plurality of bit lines. For each memory cell in a subset of the plurality of memory cells, none of the plurality of program nodes is coupled to the drain terminal of the transistor to program the each memory cell in the subset of the plurality of memory cells to store at least one data bit, the at least one data bit is most occurred between the data bits.


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