The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2017

Filed:

May. 31, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Hema Ramamurthy, Austin, TX (US);

Sanjay Parihar, Austin, TX (US);

Jongsin Yun, Austin, TX (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/41 (2006.01); G11C 11/412 (2006.01); H01L 27/11 (2006.01); G11C 11/419 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
G11C 11/412 (2013.01); G11C 11/419 (2013.01); H01L 27/1104 (2013.01); H01L 27/1112 (2013.01); H01L 27/1203 (2013.01);
Abstract

A memory device having a memory cell comprising NMOS only transistors. An SRAM bit cell comprises a first pass gate (PG) NMOS transistor coupled to a first bit line signal and a word line signal; a second PG NMOS transistor coupled to a second bit line signal and the word line signal; a first pull down (PD) NMOS transistor operatively coupled to the first PG NMOS transistor; a second PD NMOS transistor operatively coupled to the second PG NMOS transistor; a first pull up (PU) NMOS transistor operatively coupled to the first PD NMOS transistor; and a second PU NMOS transistor operatively coupled to the second PD NMOS transistor. Each of the back gates of the first and second PU NMOS transistors are coupled to a predetermined voltage signal for biasing the first and second PU NMOS transistors.


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