The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9798352 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 24, 2017

Filed:

Nov. 12, 2015
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Amitava Majumdar, San Jose, CA (US);

Balakrishna Jayadev, San Jose, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/317 (2006.01); G01R 31/3185 (2006.01); G06F 1/10 (2006.01);
U.S. Cl.
CPC ...
G06F 1/10 (2013.01); G01R 31/31704 (2013.01); G01R 31/31705 (2013.01); G01R 31/31726 (2013.01); G01R 31/318536 (2013.01); G01R 31/318583 (2013.01);
Abstract

A circuit for implementing a scan chain in an integrated circuit having a clock domain crossing is described. The circuit comprises a first dual-edge storage circuit configured to receive an input signal at a scan input and to receive a first clock signal in a first clock domain at a clock input; a storage element having a data input configured to receive an output of the first dual-edge storage circuit; a second dual-edge storage circuit configured to receive an output of the storage element at a scan input and to receive a second clock signal in a second clock domain at a clock input; and a pulse generator configured to provide, to a clock input of the storage element, a pulse signal having a pulse width selected to enable the second dual-edge storage element to store the output of the first dual-edge storage element.


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