The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2017

Filed:

Mar. 21, 2017
Applicant:

Innoaxis Co., Ltd, Namyangju-si, Gyeonggi-do, KR;

Inventor:

Hwi-Cheol Kim, Seoul, KR;

Assignee:

INNOAXIS CO., LTD, Namyangju-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/78 (2006.01); H03M 7/00 (2006.01); H03K 19/0185 (2006.01); G11C 19/00 (2006.01); G09G 3/20 (2006.01);
U.S. Cl.
CPC ...
H03M 1/785 (2013.01); G09G 3/2092 (2013.01); G11C 19/00 (2013.01); H03K 19/018521 (2013.01); H03M 7/00 (2013.01); G09G 2300/0828 (2013.01); G09G 2300/0871 (2013.01);
Abstract

A level shifter, a digital-to-analog converter (DAC), and a buffer amplifier, and a source driver and an electronic device including the same are provided. The source driver includes a level shifter configured to receive digital bits and provide a level-shifted output signal; a DAC including a resistor string configured to provide a plurality of gradation voltages formed by an upper limit voltage and a lower limit voltage being received through one end and the other end, and an N-type metal oxide semiconductor (NMOS) switch and a P-type MOS (PMOS) switch configured to be controlled by the level-shifted output signal and output a gradation voltage corresponding to the level-shifted output signal; and an amplifier configured to amplify a signal provided by the digital-to-analog converter, and the lower limit voltage is provided to a body electrode of the NMOS switch.


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