The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2017

Filed:

Jul. 01, 2016
Applicant:

Seoul Viosys Co., Ltd., Ansan-si, KR;

Inventors:

Won Cheol Seo, Ansan-si, KR;

Dae Sung Cho, Ansan-si, KR;

Kyung Hee Ye, Ansan-si, KR;

Kyoung Wan Kim, Ansan-si, KR;

Yeo Jin Yoon, Ansan-si, KR;

Assignee:

Seoul Viosys Co., Ltd., Ansan-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 33/38 (2010.01); H01L 33/08 (2010.01); H01L 33/20 (2010.01); H01L 33/44 (2010.01); H01L 33/42 (2010.01); H01L 33/62 (2010.01); H01L 33/32 (2010.01);
U.S. Cl.
CPC ...
H01L 33/387 (2013.01); H01L 33/08 (2013.01); H01L 33/20 (2013.01); H01L 33/32 (2013.01); H01L 33/38 (2013.01); H01L 33/385 (2013.01); H01L 33/42 (2013.01); H01L 33/44 (2013.01); H01L 33/62 (2013.01); H01L 2924/0002 (2013.01); H01L 2933/0016 (2013.01);
Abstract

A substrate, a first conductive type semiconductor layer arranged on the substrate, a second conductive type semiconductor layer arranged on the first conductive type semiconductor layer, an active layer disposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer, a first electrode pad electrically connected to the first conductive type semiconductor layer, a second electrode pad arranged on the second conductive type semiconductor layer, an insulation layer disposed between the second conductive type semiconductor layer and the second electrode pad, and at least one upper extension electrically connected to the second electrode pad, the at least one upper extension being electrically connected to the second conductive type semiconductor layer.


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