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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9793377 B1

PDFFull Text
Date of Patent:
Oct. 17, 2017

Filed:

Jul. 24, 2015

Thin film transistor, thin film transistor array panel including the same, and manufacturing method thereof

Applicant:

Samsung Display Co., Ltd., Yongin, KR;

Inventors:

Je Hun Lee, Seoul, KR;

Jun Ho Song, Seongnam-si, KR;

Yun Jong Yeo, Seoul, KR;

Hwa Dong Jung, Seoul, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:

H.C. Park & Associates, PLC

Primary Examiner:

Marc Armand

Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 29/40 (2006.01); H01L 21/28 (2006.01); H01L 21/268 (2006.01); H01L 21/308 (2006.01); H01L 21/02 (2006.01); H01L 27/12 (2006.01); H01L 29/423 (2006.01); H01L 29/08 (2006.01); H01L 29/86 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66742 (2013.01); H01L 21/02205 (2013.01); H01L 21/2686 (2013.01); H01L 21/28247 (2013.01); H01L 21/3086 (2013.01); H01L 27/1214 (2013.01); H01L 29/0847 (2013.01); H01L 29/401 (2013.01); H01L 29/42356 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78693 (2013.01); H01L 29/86 (2013.01);
Abstract

The present invention relates to a thin film transistor, a thin film transistor array panel, and a manufacturing method thereof. A thin film transistor according to an exemplary embodiments of the present invention includes: a gate electrode; a gate insulating layer positioned on or under the gate electrode; a channel region overlapping the gate electrode, the gate insulating layer interposed between the channel region and the gate electrode; and a source region and a drain region, facing each other with respect to the channel region, positioned in the same layer as the channel region, and connected to the channel region, wherein the channel region, the source region, and the drain region comprise an oxide semiconductor, and wherein a carrier concentration of the source region and the drain region is larger than a carrier concentration of the channel region.

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