The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9793275 B1

Date of Patent:

Oct. 17, 2017

Filed:

Aug. 14, 2009

Multilayer circuit

Applicants:

Dmitri Borisovich Strukov, Mountain View, CA (US);

Julien Borghetti, Mountain View, CA (US);

Inventors:

Dmitri Borisovich Strukov, Mountain View, CA (US);

Julien Borghetti, Mountain View, CA (US);

Assignee:

Hewlett Packard Enterprise Development LP, Houston, TX (US);

Attorney:

Fabian VanCott

Primary Examiner:

Dzung Tran

Int. Cl.

CPC ...

H01L 23/48 (2006.01); H01L 29/792 (2006.01); H01L 23/52 (2006.01); H01L 21/44 (2006.01); H01L 27/105 (2006.01); H01L 27/06 (2006.01); H01L 27/10 (2006.01); H01L 27/112 (2006.01); H01L 27/24 (2006.01);

U.S. Cl.

CPC ...

H01L 27/105 (2013.01); H01L 27/0688 (2013.01); H01L 27/101 (2013.01); H01L 27/112 (2013.01); H01L 27/11286 (2013.01); H01L 27/24 (2013.01);

Abstract

A multilayer circuit () includes a base layer () which has a number of base vias (), a first overlying layer () formed on the base layer () and having a first routing section () and a second overlying layer () formed on the first overlying layer (). The second overlying layer () has a second routing section () and is formed using the same set of masks. The first routing section () and the second routing section () form a unique electrical pathway () between a base via () and an element in an overlying layer. A method for forming a multilayer circuit is also provided.

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