The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2017

Filed:

Sep. 15, 2016
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Masaki Shiraishi, Hitachi, JP;

Tomoaki Uno, Takasaki, JP;

Nobuyoshi Matsuura, Takasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 29/78 (2006.01); H02M 7/00 (2006.01); H01L 21/28 (2006.01); H01L 21/8234 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H02M 3/155 (2006.01); H01L 29/10 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/872 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0629 (2013.01); H01L 21/28035 (2013.01); H01L 21/823475 (2013.01); H01L 23/3107 (2013.01); H01L 23/49524 (2013.01); H01L 23/49562 (2013.01); H01L 23/49575 (2013.01); H01L 24/06 (2013.01); H01L 24/40 (2013.01); H01L 24/49 (2013.01); H01L 24/73 (2013.01); H01L 29/4236 (2013.01); H01L 29/45 (2013.01); H01L 29/4916 (2013.01); H01L 29/66143 (2013.01); H01L 29/66734 (2013.01); H01L 29/7806 (2013.01); H01L 29/7813 (2013.01); H02M 3/155 (2013.01); H02M 7/003 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 29/1095 (2013.01); H01L 29/41741 (2013.01); H01L 29/4232 (2013.01); H01L 29/4238 (2013.01); H01L 29/456 (2013.01); H01L 29/872 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/40095 (2013.01); H01L 2224/40245 (2013.01); H01L 2224/40247 (2013.01); H01L 2224/45015 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/48011 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48095 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/48253 (2013.01); H01L 2224/48624 (2013.01); H01L 2224/4903 (2013.01); H01L 2224/49051 (2013.01); H01L 2224/49111 (2013.01); H01L 2224/49171 (2013.01); H01L 2224/49175 (2013.01); H01L 2224/73221 (2013.01); H01L 2924/01002 (2013.01); H01L 2924/01004 (2013.01); H01L 2924/014 (2013.01); H01L 2924/0105 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01014 (2013.01); H01L 2924/01015 (2013.01); H01L 2924/01021 (2013.01); H01L 2924/01022 (2013.01); H01L 2924/01023 (2013.01); H01L 2924/01027 (2013.01); H01L 2924/01028 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01046 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/01057 (2013.01); H01L 2924/01072 (2013.01); H01L 2924/01074 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/12032 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1532 (2013.01); H01L 2924/181 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19043 (2013.01); H01L 2924/20753 (2013.01); H01L 2924/20755 (2013.01); H01L 2924/3011 (2013.01); H01L 2924/30105 (2013.01); H01L 2924/30107 (2013.01);
Abstract

In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.


Find Patent Forward Citations

Loading…