The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2017

Filed:

Jun. 08, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Yong Kong Siew, Suwon-si, KR;

Hyunsu Kim, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76871 (2013.01); H01L 21/7682 (2013.01); H01L 21/76802 (2013.01); H01L 21/76832 (2013.01); H01L 21/76834 (2013.01); H01L 21/76858 (2013.01); H01L 21/76865 (2013.01); H01L 21/76877 (2013.01);
Abstract

A method of fabricating a semiconductor device, the method including forming at least one interconnection structure that includes a metal interconnection and a first insulating pattern sequentially stacked on a substrate; forming barrier patterns covering sidewalls of the interconnection structure; forming second insulating patterns at sides of the interconnection structure, the second insulating patterns being spaced apart from the interconnection structure with the barrier patterns interposed therebetween; forming a via hole in the first insulating pattern by etching a portion of the first insulating pattern, the via hole exposing a top surface of the metal interconnection and sidewalls of the barrier patterns; and forming a via in the via hole.


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