The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2017

Filed:

Jan. 06, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Rodrigo Alvarez-Icaza Rivera, San Jose, CA (US);

John V. Arthur, Mountain View, CA (US);

John E. Barth, Jr., Williston, VT (US);

Andrew S. Cassidy, San Jose, CA (US);

Subramanian S. Iyer, Mount Kisco, NY (US);

Bryan L. Jackson, Fremont, CA (US);

Paul A. Merolla, Palo Alto, CA (US);

Dharmendra S. Modha, San Jose, CA (US);

Jun Sawada, Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 15/80 (2006.01);
U.S. Cl.
CPC ...
G06F 15/80 (2013.01); G06F 13/4022 (2013.01); G06F 13/4068 (2013.01);
Abstract

Embodiments of the invention relate to an array of processor core circuits with reversible tiers. One embodiment comprises multiple tiers of core circuits and multiple switches for routing packets between the core circuits. Each tier comprises at least one core circuit. Each switch comprises multiple router channels for routing packets in different directions relative to the switch, and at least one routing circuit configured for reversing a logical direction of at least one router channel.


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