The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2017

Filed:

Sep. 22, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

John K. Debrosse, Colchester, VT (US);

Blake G. Fitch, Croton-On-Hudson, NY (US);

Michele M. Franceschini, White Plains, NY (US);

Todd E. Takken, Brewster, NY (US);

Daniel C. Worledge, Cortlandt Manor, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); G06F 3/06 (2006.01); G11C 7/10 (2006.01); G11C 13/00 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0613 (2013.01); G06F 3/061 (2013.01); G06F 3/0602 (2013.01); G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 3/0679 (2013.01); G06F 3/0688 (2013.01); G06F 13/1668 (2013.01); G11C 7/10 (2013.01); G11C 7/1003 (2013.01); G11C 7/1015 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/1693 (2013.01); G11C 13/004 (2013.01); G11C 13/0004 (2013.01); G11C 13/0061 (2013.01); G11C 13/0069 (2013.01);
Abstract

A memory includes multiple non-volatile memory devices, each having multiple nonvolatile memory cells. A write controller is configured to stream bits to the memory devices using a write data channel that optimizes a speed of writing to the memory devices to provide writes at a first speed. A read controller is configured to read bits from the memory devices, at a second speed slower than the first speed, using a read channel. A bi-directional bus that both the write controller and the self-referenced read controller share to access the plurality of non-volatile memory devices.


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