The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2017

Filed:

Aug. 11, 2016
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Sung-Eun Lee, Gyeonggi-do, KR;

Kyung-Hoon Kim, Gyeonggi-do, KR;

Myeong-Jae Park, Gyeonggi-do, KR;

Woo-Yeol Shin, Gyeonggi-do, KR;

Han-Kyu Chi, Gyeonggi-do, KR;

Yong-Ju Kim, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/159 (2006.01); H03K 21/38 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/159 (2013.01); H03K 21/38 (2013.01); H03K 2005/00078 (2013.01); H03K 2005/00273 (2013.01);
Abstract

A delay circuit includes: a plurality of delay units that are serially coupled with each other in a form of loop and sequentially delay an input signal of the delay circuit; an input control unit that selects a delay unit to receive the input signal of the delay circuit among the plurality of the delay units; and an output control unit that controls an output signal of a predetermined delay unit among the plurality of the delay units to be outputted as an output signal of the delay circuit, when the output signal of the predetermined delay unit is enabled N times, where N is an integer equal to or greater than 0.


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