The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2017

Filed:

Aug. 23, 2012
Applicants:

Shogo Yamagishi, Hamamatsu, JP;

Masatoshi Fujimoto, Hamamatsu, JP;

Akira Takahashi, Hamamatsu, JP;

Inventors:

Shogo Yamagishi, Hamamatsu, JP;

Masatoshi Fujimoto, Hamamatsu, JP;

Akira Takahashi, Hamamatsu, JP;

Assignee:

HAMAMATSU PHOTONICS K.K., Hamamatsu-shi, Shizuoka, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02J 7/34 (2006.01); H02J 1/10 (2006.01); H02J 3/38 (2006.01); H02M 7/537 (2006.01); H03K 4/02 (2006.01); G02F 1/03 (2006.01); H01S 3/23 (2006.01); H03K 17/691 (2006.01); H03K 17/687 (2006.01); H01S 3/08 (2006.01); H01S 3/107 (2006.01); H01S 3/00 (2006.01); H03K 17/10 (2006.01);
U.S. Cl.
CPC ...
H02M 7/537 (2013.01); G02F 1/0327 (2013.01); H01S 3/235 (2013.01); H03K 4/023 (2013.01); H01S 3/0057 (2013.01); H01S 3/0064 (2013.01); H01S 3/08 (2013.01); H01S 3/1075 (2013.01); H03K 17/102 (2013.01); H03K 17/691 (2013.01); H03K 2017/6875 (2013.01); H03K 2217/009 (2013.01); Y10T 307/549 (2015.04);
Abstract

A driving circuit is a circuit selectively outputting one of a staircase wave and a square wave from an output terminal, to drive a capacitive load, and includes a first power source supplying a constant voltage VH, a first FET connected between the output terminal and the first power source, a first transformer in which an output side coil is connected to a gate of the first FET, a first input terminal connected to an input side coil of the first transformer via a capacitive element, a second power source supplying a constant voltage VL, a second FET connected between the output terminal and the second power source, a second transformer in which an output side coil is connected to a gate of the second FET, and a second input terminal connected to an input side coil of the second transformer via a capacitive element.


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