The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2017

Filed:

Apr. 23, 2014
Applicant:

Upi Semiconductor Corp., Hsinchu County, TW;

Inventor:

Wei-Ling Chen, Hsinchu County, TW;

Assignee:

uPI Semiconductor Corp., Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01); H02M 3/158 (2006.01); H02M 1/00 (2006.01);
U.S. Cl.
CPC ...
H02M 3/158 (2013.01); H02M 2001/0006 (2013.01); H03K 2217/0063 (2013.01); H03K 2217/0072 (2013.01); H03K 2217/0081 (2013.01);
Abstract

A driver and a driving control method for a power converter are provided. The driver includes a level shift circuit, a negative voltage generator and a first PMOS transistor. The level shift circuit provides an output signal, wherein the output signal has a first operation voltage and a second operation voltage. When the output signal received by the negative voltage generator is the first operation voltage, the negative voltage generator outputs the first operation voltage. When the output signal received by the negative voltage generator is the second operation voltage, the negative voltage generator generates and outputs a third operation voltage, and the third operation voltage is lower than the second operation voltage. A control terminal of the first PMOS transistor is coupled to an output terminal of the negative voltage generator. An output terminal of the first PMOS transistor provides a driving voltage.


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