The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 10, 2017
Filed:
Feb. 13, 2015
Applicant:
SK Hynix Inc., Icheon-Si, KR;
Inventors:
Min-Suk Lee, Icheon-Si, KR;
Chan-Sik Park, Icheon-Si, KR;
Jae-Heon Kim, Icheon-Si, KR;
Choi-Dong Kim, Icheon-Si, KR;
Assignee:
SK hynix Inc., Icheon-Si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); H01L 43/12 (2006.01); H01L 43/08 (2006.01); H01L 45/00 (2006.01); H01L 27/108 (2006.01); G06F 13/00 (2006.01); H01L 27/11 (2006.01); H01L 27/11507 (2017.01);
U.S. Cl.
CPC ...
H01L 43/12 (2013.01); H01L 27/108 (2013.01); H01L 43/08 (2013.01); H01L 45/04 (2013.01); H01L 45/06 (2013.01); H01L 45/1233 (2013.01); H01L 45/141 (2013.01); H01L 45/16 (2013.01); H01L 27/11 (2013.01); H01L 27/11507 (2013.01);
Abstract
An electronic device including a semiconductor memory is provided. The semiconductor memory includes an interlayer dielectric layer disposed over a substrate, and having a recess which exposes a portion of the substrate; a bottom contact partially filling the recess; and a resistance variable element including a bottom layer which fills at least a remaining space of the recess over the bottom contact, and a remaining layer which is disposed over the bottom layer and protrudes out of the interlayer dielectric layer.