The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2017

Filed:

Dec. 22, 2014
Applicant:

Canon Kabushiki Kaisha, Tokyo, JP;

Inventors:

Ryota Sekiguchi, Tokyo, JP;

Toshihiko Ouchi, Machida, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01N 21/3581 (2014.01); H01L 31/112 (2006.01); H01L 29/872 (2006.01); H01L 27/06 (2006.01); H01L 31/108 (2006.01); H01L 31/18 (2006.01); H01L 29/66 (2006.01); G01J 1/44 (2006.01); H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
H01L 31/1123 (2013.01); G01J 1/44 (2013.01); H01L 27/0629 (2013.01); H01L 27/1463 (2013.01); H01L 27/14649 (2013.01); H01L 27/14689 (2013.01); H01L 29/66143 (2013.01); H01L 29/872 (2013.01); H01L 31/1085 (2013.01); H01L 31/1804 (2013.01); G01J 2001/4446 (2013.01); G01N 21/3581 (2013.01); Y02E 10/547 (2013.01); Y02P 70/521 (2015.11);
Abstract

A semiconductor device includes a silicon substrate and a detection element and p-type and n-type MOS transistors, which are arranged on the silicon substrate, wherein the detection element includes a semiconductor layer, electrodes, and a Schottkey barrier disposed therebetween, the semiconductor layer is arranged just above a layer having the same composition and height as those of an impurity diffusion layer in the source or drain of the p-type or n-type MOS transistor, a region, in the silicon substrate, having the same composition and height as those of a channel region, in the silicon substrate, just below a gate oxide film of the p-type MOS transistor or the n-type MOS transistor, or a region, in the silicon substrate, having the same composition and height as those of a region just below a field oxide film disposed between the p-type and the n-type MOS transistor.


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