The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 10, 2017
Filed:
Mar. 10, 2015
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventor:
Jang Uk Lee, Gyeonggi-do, KR;
Assignee:
SK Hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66666 (2013.01); H01L 21/2815 (2013.01); H01L 29/401 (2013.01); H01L 29/4236 (2013.01); H01L 29/42368 (2013.01); H01L 29/7827 (2013.01);
Abstract
A semiconductor device includes a gate electrode formed on a sidewall of a structure extending from a semiconductor substrate. A junction region is form in the structure to a first depth from a top of the structure and formed to overlap the gate electrode. A protection layer is formed between an outer wall of the structure and the gate electrode to a second depth less than the first depth from the top of the structure.
Lee, Jang. (2017). Methods of fabricating transistors with a protection layer to improve the insulation between a gate electrode and a junction region (U.S. Patent No. 9786766). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9786766
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile