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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9786735 B1

PDFFull Text
Date of Patent:
Oct. 10, 2017

Filed:

Dec. 14, 2015

Semiconductor device and method of manufacturing the same

Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Akio Ichimura, Ibaraki, JP;

Satoshi Eguchi, Ibaraki, JP;

Tetsuya Iida, Ibaraki, JP;

Yuya Abiko, Ibaraki, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Tokyo, JP;

Attorney:

Mattingly & Malur, PC

Primary Examiner:

Mark Tornow

Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0634 (2013.01); H01L 29/66712 (2013.01); H01L 29/7811 (2013.01); H01L 29/1095 (2013.01); H01L 29/404 (2013.01); H01L 29/41766 (2013.01); H01L 29/66727 (2013.01);
Abstract

A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.

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