The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2017

Filed:

Feb. 28, 2017
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Mari Matsumoto, Kawasaki, JP;

Shinichi Yasuda, Setagaya, JP;

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 17/16 (2006.01); H01L 27/118 (2006.01); H01L 27/02 (2006.01); H01L 23/525 (2006.01); H01L 27/112 (2006.01);
U.S. Cl.
CPC ...
G11C 17/16 (2013.01); H01L 23/5252 (2013.01); H01L 27/0207 (2013.01); H01L 27/11206 (2013.01); H01L 27/11807 (2013.01); H01L 2027/11866 (2013.01); H01L 2027/11885 (2013.01);
Abstract

A memory element according to an embodiment includes: first through fourth impurity layers arranged in a semiconductor layer including first to third portions; a first gate wiring line disposed on the first portion located between the first and second impurity layers; a second gate wiring line disposed on the second portion located between the second and third impurity layers; a third gate wiring line disposed on the third portion located between the third and fourth impurity layers; a first insulating layer disposed between the first portion and the first gate wiring line; a second insulating layer disposed between the second portion and the second gate wiring line; a third insulating layer disposed between the third portion and the third gate wiring line; first wiring line electrically connected to the first through third gate wiring lines; and second wiring line electrically connected to the first through fourth impurity layers.


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