The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2017

Filed:

Aug. 16, 2013
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Beijing Boe Optoelectronics Technology Co., Ltd., Beijing, CN;

Inventors:

Hao Wu, Beijing, CN;

Hongjun Yu, Beijing, CN;

Xiuqiang Zhao, Beijing, CN;

Ziwei Cui, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/038 (2013.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3688 (2013.01); G09G 3/3659 (2013.01); G09G 3/3677 (2013.01); G09G 2300/043 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0252 (2013.01);
Abstract

A pixel driving circuit and driving method thereof, an array substrate and a display device. The pixel driving circuit can maintain a voltage difference between two terminals of a storage capacitor (Cst) when a gate line scanning is ended. The pixel driving circuit comprises a pixel thin film transistor (T) and a storage capacitor (Cst), wherein a gate of the pixel thin film transistor (T) is connected to a gate line, a first terminal of the pixel thin film transistor (T) is connected to a data signal (Data), a second terminal of the pixel thin film transistor (T) is connected to a first terminal of the storage capacitor and a second terminal of the storage capacitor (Cst) is grounded. The pixel driving circuit further comprises a follow module connected the first terminal of the storage capacitor (Cst), and configured to maintain a voltage difference between two terminals of the storage capacitor (Cst) when a gate scanning signal (Gate(n)) makes a transition from a high level to a low level, so as to enable the pixel electrode to obtain sufficient voltage thereby ensuring the display effect of the liquid crystal display.


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