Gate driving circuit and display apparatus including the same

Abstract

A gate driving circuit includes a plurality of stages for providing gate signals, wherein a k-th stage (k is a natural number greater than 3) includes a first output transistor including a control electrode connected to a first node, an input electrode for receiving a clock signal, and an output electrode for outputting a k-th gate signal, a second output transistor including a control electrode connected to the first node, an input electrode for receiving the clock signal, and an output electrode for outputting a k-th carry signal, a pull-down unit connected to a discharge node to pull down the output electrode of the first output transistor in response to a signal of the discharge node, and a discharge unit configured to output a (k−1)-th carry signal output from a (k−1)-th stage to the discharge node in response to a (k+1)-th carry signal output from a (k+1)-th stage.