The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2017

Filed:

Jul. 22, 2015
Applicant:

Huawei Technologies Co., Ltd., Shenzhen, CN;

Inventor:

Ge Du, Chengdu, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/30 (2006.01); G06F 13/40 (2006.01); G06F 11/22 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 11/3027 (2013.01); G06F 11/221 (2013.01); G06F 13/4022 (2013.01); G06F 13/4221 (2013.01);
Abstract

In a Peripheral Component Interconnect Express (PCIe) system, a first PCIe apparatus determines that at least one of lanes of a link between the first PCIe apparatus and a second PCIe apparatus is disabled, wherein the link includes M lanes numbered in a first order. Based upon the determination, the first PCIe apparatus obtains a number N indicating a number of available lanes of the link by performing a lane negotiation with the second PCIe apparatus. Then, a processor determines that N<M/2. Based upon the determination, the first PCIe apparatus re-numbers at least some of the lanes of the link in a reverse order opposite to the first order as instructed by the processor. At last, the first PCIe apparatus continue to perform a negotiation with the second PCIe apparatus to obtain available lanes.


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