The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2017

Filed:

Jan. 20, 2017
Applicants:

Yuuya Miyoshi, Osaka, JP;

Tohru Kanno, Osaka, JP;

Inventors:

Yuuya Miyoshi, Osaka, JP;

Tohru Kanno, Osaka, JP;

Assignee:

Ricoh Company, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 1/04 (2006.01); H04N 1/00 (2006.01);
U.S. Cl.
CPC ...
H04N 1/00013 (2013.01); H04N 1/00907 (2013.01); H04N 1/0461 (2013.01); H04N 2201/0081 (2013.01); H04N 2201/0094 (2013.01);
Abstract

A solid-state imaging device includes a pixel circuit including a plurality of photoelectric conversion elements and configured to output a signal level and a reset level, an analog correlated double sampling (CDS) circuit connected to the pixel circuit and configured to perform correlated double sampling in an analog region based on the signal level and the reset level and output a result of the correlated double sampling, an analog-digital (AD) conversion circuit connected to the analog CDS circuit and configured to convert two different analog signals output from the analog CDS circuit into two digital signals, a signal processing circuit connected to the AD conversion circuit and configured to obtain a difference between the two different digital signals output from the AD conversion circuit; and a reference voltage generating circuit to output a first reference voltage that defines a clamp level of the analog CDS circuit.


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