The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2017
Filed:
Apr. 13, 2016
Applicant:
Macom Technology Solutions Holdings, Inc., Lowell, MA (US);
Inventor:
Kohei Fujii, San Jose, CA (US);
Assignee:
MACOM Technology Solutions Holdings, Inc., Lowell, MA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/60 (2006.01); H03F 3/193 (2006.01); H03F 3/213 (2006.01); H03F 1/22 (2006.01); H03F 1/02 (2006.01); H03F 1/07 (2006.01);
U.S. Cl.
CPC ...
H03F 3/607 (2013.01); H03F 3/193 (2013.01); H03F 3/213 (2013.01); H03F 1/0288 (2013.01); H03F 1/07 (2013.01); H03F 1/22 (2013.01); H03F 1/223 (2013.01); H03F 3/60 (2013.01); H03F 2200/153 (2013.01); H03F 2200/61 (2013.01); H03F 2200/75 (2013.01);
Abstract
An apparatus includes an input port, an output port, and a plurality of amplifier stages connected in parallel between the input port and the output port. Each of the amplifier stages comprises a common source field effect transistor (CSFET) and at least two common gate field effect transistors (CGFETs) coupled in series with a drain of the common source FET. At least one of the common gate field effect transistors of each stage includes a stabilizing network connected between drain and source diffusions.