The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2017

Filed:

Sep. 22, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventor:

Doowon Kwon, Seongnam-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H04N 5/225 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14634 (2013.01); H01L 23/49827 (2013.01); H01L 23/5226 (2013.01); H01L 24/32 (2013.01); H01L 25/0657 (2013.01); H01L 27/1462 (2013.01); H01L 27/14618 (2013.01); H01L 27/14645 (2013.01); H04N 5/2253 (2013.01); H01L 27/1464 (2013.01); H01L 27/1469 (2013.01); H01L 27/14621 (2013.01); H01L 27/14627 (2013.01); H01L 27/14636 (2013.01); H01L 2224/32105 (2013.01); H01L 2224/32146 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48237 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/06544 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A device includes a first integrated circuit substrate including a plurality of first metal layers interconnected by first vias and a second integrated circuit substrate on the first integrated circuit substrate and including second metal layers interconnected by second vias. An insulation layer is disposed between the first and second substrates and a connection region is disposed in the insulation layer and electrically connects a first one of the first metal layers to a first one of the second metal layers. The device further includes a bonding pad on the second substrate and a through via extending from the bonding pad and into the second to contact a second one of the second metal layers. The through via is positioned so as to not overlap at least one of the first vias, the second vias and the connection region. Methods of fabricating such device are also described.


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