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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9780113 B1

PDFFull Text
Date of Patent:
Oct. 03, 2017

Filed:

Dec. 09, 2015

Method for fabricating semiconductor device including a first ild with sloped surface on a stacked structure and a second ild on the first ild

Applicants:

Jiwoon Im, Hwaseong-si, KR;

Kwangchul Park, Suwon-si, KR;

Jiyoun Seo, Seoul, KR;

Jongmyeong Lee, Seongnam-si, KR;

Kyung-tae Jang, Seoul, KR;

Byungho Chun, Seongnam-si, KR;

Won-seok Jung, Anyang-si, KR;

Jongwan Choi, Suwon-si, KR;

Tae-jong Han, Seoul, KR;

Inventors:

Jiwoon Im, Hwaseong-si, KR;

Kwangchul Park, Suwon-si, KR;

Jiyoun Seo, Seoul, KR;

Jongmyeong Lee, Seongnam-si, KR;

Kyung-Tae Jang, Seoul, KR;

Byungho Chun, Seongnam-si, KR;

Won-Seok Jung, Anyang-si, KR;

Jongwan Choi, Suwon-si, KR;

Tae-Jong Han, Seoul, KR;

Assignee:

Samsung Electronics Co., Ltd., Gyeonggi-do, KR;

Attorney:

Harness, Dickey & Pierce, P.L.C.

Primary Examiner:

Cory Eskridge

Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 27/11582 (2017.01); H01L 27/1157 (2017.01); H01L 27/11575 (2017.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/76837 (2013.01); H01L 27/1157 (2013.01); H01L 27/11575 (2013.01);
Abstract

A method for fabricating a semiconductor device includes forming a stacked structure on a substrate, forming a first interlayer dielectric covering the stacked structure, and forming a second interlayer dielectric covering the first interlayer dielectric. The stacked structure includes a stepwise shape. The first interlayer dielectric includes at least one step portion having a slope surface connecting a first top surface to a second top surface. The first top surface and the sloped surface define a first angle that is an obtuse angle. A level of the second top surface is higher than a level of the first top surface.

Find Patent Forward Citations

Im, Jiwoon. (2017). Method for fabricating semiconductor device including a first ild with sloped surface on a stacked structure and a second ild on the first ild (U.S. Patent No. 9780113). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9780113

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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