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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9780060 B1

PDFFull Text
Date of Patent:
Oct. 03, 2017

Filed:

Dec. 02, 2016

Packaged ic with solderable sidewalls

Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Yong Lin, Plano, TX (US);

Vikas Gupta, Dallas, TX (US);

Rongwei Zhang, Dallas, TX (US);

Assignee:

TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);

Attorneys:

Rose Alyssa Keagy

Charles A. Brill

Frank D. Cimino

Primary Examiner:

Ngan Ngo

Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/495 (2006.01); H01L 23/31 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/544 (2006.01); H01L 21/304 (2006.01);
U.S. Cl.
CPC ...
H01L 24/29 (2013.01); H01L 21/304 (2013.01); H01L 21/4825 (2013.01); H01L 21/565 (2013.01); H01L 21/78 (2013.01); H01L 23/3114 (2013.01); H01L 23/4952 (2013.01); H01L 23/49503 (2013.01); H01L 23/49541 (2013.01); H01L 23/544 (2013.01); H01L 24/27 (2013.01); H01L 2221/68327 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54453 (2013.01); H01L 2224/2732 (2013.01); H01L 2224/27318 (2013.01); H01L 2224/27848 (2013.01); H01L 2224/29034 (2013.01); H01L 2224/29111 (2013.01); H01L 2224/29139 (2013.01); H01L 2224/29144 (2013.01); H01L 2224/29147 (2013.01); H01L 2224/29155 (2013.01); H01L 2224/29164 (2013.01); H01L 2224/29169 (2013.01);
Abstract

A packaged IC wherein a portion of the sidewalls of the packaged IC are solderable metal. A method of forming a packaged IC wherein a portion of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal. A method of forming a packaged IC wherein all of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal and a portion of sidewall of the molding compound is solderable metal.

Find Patent Forward Citations

Lin, Yong. (2017). Packaged ic with solderable sidewalls (U.S. Patent No. 9780060). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9780060

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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