The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9780040 B1

Date of Patent:

Oct. 03, 2017

Filed:

Aug. 07, 2014

Integrated circuit package substrates having a common die dependent region and methods for designing the same

Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Siow Chek Tan, Gurun, MY;

Swee Fong Chong, Balik Pulau, MY;

Pheak Ti Teh, Tanjung Bungah, MY;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:

Vineet Dixit

Primary Examiner:

Marc Armand

Assistant Examiner:

Younes Boulghassoul

Int. Cl.

CPC ...

G06F 17/50 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01);

U.S. Cl.

CPC ...

H01L 23/5386 (2013.01); G06F 17/5077 (2013.01); H01L 24/14 (2013.01); H01L 2224/14131 (2013.01);

Abstract

Techniques for designing integrated circuit (IC) package substrates are provided. One of the provided techniques include routing a first set of interconnects in a first region of an IC package substrate based on a first routing template and routing a second set of interconnects in a second region of the IC package substrate based on a second routing template. The first routing template is associated with output pins on the IC package substrate while the second routing template is associated with interconnects on at least one IC die of the multiple IC dies. In one scenario, the first routing template is a common routing template. As such, when a different IC die is used with an identical, or otherwise similar, IC package substrate, interconnects associated with output pins on that IC package substrate does not need to be rerouted as they may be routed based on the common routing template.

Find Patent Forward Citations

Tan, Siow. (2017). Integrated circuit package substrates having a common die dependent region and methods for designing the same (U.S. Patent No. 9780040). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9780040

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