The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2017
Filed:
Feb. 02, 2016
Applicant:
Pannova Semic, Llc, Santa Clara, CA (US);
Inventors:
Assignee:
PANNOVA SEMIC, LLC, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/535 (2006.01); H01L 29/78 (2006.01); H01L 21/285 (2006.01); H01L 21/8234 (2006.01); H01L 27/11 (2006.01); H01L 29/161 (2006.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 21/28518 (2013.01); H01L 21/28525 (2013.01); H01L 21/76895 (2013.01); H01L 21/823425 (2013.01); H01L 21/823468 (2013.01); H01L 21/823475 (2013.01); H01L 27/11 (2013.01); H01L 29/161 (2013.01); H01L 29/78 (2013.01); H01L 2924/0002 (2013.01);
Abstract
The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.