The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2017

Filed:

May. 04, 2015
Applicant:

Hrl Laboratories Llc, Malibu, CA (US);

Inventors:

Alexandros D. Margomenos, Pasadena, CA (US);

Miroslav Micovic, Thousand Oaks, CA (US);

Assignee:

HRL Laboratories, LLC, Malibu, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/367 (2006.01); H01L 23/00 (2006.01); H01L 23/36 (2006.01); H01L 21/683 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 21/6835 (2013.01); H01L 23/36 (2013.01); H01L 24/20 (2013.01); H01L 24/33 (2013.01); H01L 24/82 (2013.01); H01L 24/95 (2013.01); H01L 2224/211 (2013.01); H01L 2224/3303 (2013.01); H01L 2224/33106 (2013.01); H01L 2224/33505 (2013.01); H01L 2224/95001 (2013.01);
Abstract

A method of mounting a plurality of semiconductor or microelectronic chips or dies, the method including providing a carrier, temporarily adhering the plurality of semiconductor or microelectronic chips or dies to the carrier with active faces of the chips or dies facing towards the carrier, covering backsides of the chips and filling empty spaces between the chips or dies with a metallic material to thereby define an assembly of the chips or dies and the metallic material, and releasing the assembly from the carrier, wherein each chip or die comprises at least one bonding ring higher than a height of the active face of the respective chip or die or any connections on the active face of the respective chip or die.


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