The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2017

Filed:

Nov. 12, 2013
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Ordos Yuansheng Optoelectronics Co., Ltd., Ordos, Inner Mongolia, CN;

Inventors:

Xueguang Hao, Beijing, CN;

Seong Jun An, Beijing, CN;

Bongyeol Ryu, Beijing, CN;

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G11C 19/28 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3677 (2013.01); G09G 3/3688 (2013.01); G09G 3/3696 (2013.01); G11C 19/28 (2013.01); G09G 2300/0809 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0286 (2013.01);
Abstract

There are provided a shift register unit, a gate driving circuit and a display apparatus, which are configured to suppress interference noise due to a change of an alternating current clock signal and enhance stability of the shift register unit. The shift register unit comprises: an input module configured to charge a pull-up node in response to the input signal; a pull-down module configured to provide the low voltage signal to the pull-up node and the output terminal in response to a voltage signal of the pull-down node; a pull-down driving module configured to charge a pull-down node in response to the first clock signal and the second clock signal and discharge the pull-down node in response to the voltage signal of the pull-up node; an output module configured to provide a first clock signal to an output terminal in response to a voltage signal of the pull-up node; and a reset module configured to discharge the output terminal in response to the second clock signal.


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