The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2017

Filed:

Mar. 27, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Yanru Li, San Diego, CA (US);

Dexter Tamio Chun, San Diego, CA (US);

Alain Artieri, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 3/06 (2006.01); G06F 12/0862 (2016.01); G11C 11/406 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0625 (2013.01); G06F 1/324 (2013.01); G06F 1/3296 (2013.01); G06F 3/0611 (2013.01); G06F 3/0653 (2013.01); G06F 3/0685 (2013.01); G06F 12/0862 (2013.01); G11C 7/1072 (2013.01); G11C 11/40607 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/222 (2013.01); G06F 2212/602 (2013.01); Y02B 60/1217 (2013.01);
Abstract

Systems, methods, and computer programs are disclosed for method for reducing memory subsystem power. In an exemplary method, a system resource manager provides memory performance requirements for a plurality of memory clients to a double data rate (DDR) subsystem. The DDR subsystem and the system resource manager reside on a system on chip (SoC) electrically coupled to a dynamic random access memory (DRAM). A cache hit rate is determined of each of the plurality of memory clients associated with a system cache residing on the DDR subsystem. The DDR subsystem controls a DDR clock frequency based on the memory performance requirements received from the system resource manager and the cache hit rates of the plurality of memory clients.


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