The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2017

Filed:

Mar. 05, 2015
Applicant:

Samsung Display Co., Ltd., Yongin, Gyeonggi-do, KR;

Inventors:

Kwang-Chul Jung, Seongnam-si, KR;

Se Young Song, Hwaseong-si, KR;

Sung-Jin Hong, Hwaseong-si, KR;

Jae Byung Park, Seoul, KR;

Mee Hye Jung, Suwon-si, KR;

Hyun Min Cho, Seoul, KR;

Assignee:

Samsung Display Co., Ltd., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 5/02 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G09G 3/36 (2006.01); G02F 1/1343 (2006.01);
U.S. Cl.
CPC ...
G02F 1/13624 (2013.01); G09G 3/3648 (2013.01); G02F 1/1368 (2013.01); G02F 2001/134345 (2013.01); G09G 3/3614 (2013.01); G09G 2300/0447 (2013.01); G09G 2300/0814 (2013.01);
Abstract

A display device is disclosed. In one aspect, the display device includes a plurality of pixels each including first and second switching elements connected to a first gate line and a data line. Each pixel also includes a first memory capacitor connected to the first switching element and a capacitance voltage line, a second memory capacitor connected to the second switching element and the capacitance voltage line, and a third switching element and a fourth switching element each connected to a second gate line and a reference voltage line. Each pixel further includes a fifth switching element connected to a third gate line and the first memory capacitor, a sixth switching element connected to the third gate line and the second memory capacitor, a first subpixel electrode connected to the third and fifth switching elements, and a second subpixel electrode connected to the fourth and sixth switching element.


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