The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2017

Filed:

Dec. 15, 2015
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

DongSoo Kim, Jeollabuk-do, KR;

Hun Jeoung, Gyeonggi-do, KR;

SangHee Yu, Gyeonggi-do, KR;

SungHyun Cho, Seoul, KR;

BoSun Lee, Chungcheongbuk-do, KR;

Sungwook Chang, Gyeonggi-do, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); H03K 17/687 (2006.01); G09G 3/3225 (2016.01); G09G 3/3266 (2016.01); G11C 19/28 (2006.01); G06F 1/04 (2006.01); G09G 3/20 (2006.01);
U.S. Cl.
CPC ...
H03K 17/6871 (2013.01); G06F 1/04 (2013.01); G09G 3/2092 (2013.01); G09G 3/3225 (2013.01); G09G 3/3266 (2013.01); G09G 3/3648 (2013.01); G09G 3/3677 (2013.01); G11C 19/28 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0809 (2013.01); G09G 2310/0224 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0214 (2013.01);
Abstract

A gate driver and a display device including the gate driver are provided which can prevent an abnormal output of a gate-high voltage from a stage by stably maintaining a discharge potential of a pull-up node. The gate driver includes a plurality of stages, and each stage includes a pull-up transistor that outputs a clock signal input to a first clock terminal to an output terminal depending on a voltage of a pull-up node; a pull-down transistor that outputs a first source voltage input to a first source voltage terminal to the output terminal depending on a voltage of a pull-down node; and a first noise removing unit that supplies a gate-off voltage to the pull-up node to remove noise of the pull-up node in response to the clock signal input to the first clock terminal.


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