The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2017

Filed:

Aug. 18, 2014
Applicant:

Sumitomo Electric Industries, Ltd., Osaka-shi, JP;

Inventors:

Kei Fujii, Itami, JP;

Koji Nishizuka, Itami, JP;

Takashi Kyono, Itami, JP;

Kaoru Shibata, Itami, JP;

Katsushi Akita, Itami, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 31/00 (2006.01); H01L 31/0352 (2006.01); H01L 21/02 (2006.01); H01L 31/0304 (2006.01); H01L 31/18 (2006.01);
U.S. Cl.
CPC ...
H01L 31/035236 (2013.01); H01L 21/0262 (2013.01); H01L 21/02392 (2013.01); H01L 21/02461 (2013.01); H01L 21/02463 (2013.01); H01L 21/02466 (2013.01); H01L 21/02507 (2013.01); H01L 21/02546 (2013.01); H01L 31/03042 (2013.01); H01L 31/03046 (2013.01); H01L 31/1832 (2013.01); Y02E 10/544 (2013.01); Y02P 70/521 (2015.11);
Abstract

An epitaxial wafer which allows manufacture of a photodiode having suppressed dark current and ensured sensitivity, and a method for manufacturing the epitaxial wafer, are provided. The epitaxial wafer of the present invention includes: a III-V semiconductor substrate; and a multiple quantum well structure disposed on the substrate, and including a plurality of pairs of a first layer and a second layer. The total concentration of elements contained as impurities in the multiple quantum well structure is less than or equal to 5×10cm.


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