The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2017

Filed:

Apr. 02, 2016
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Masao Uchida, Osaka, JP;

Kouichi Saitou, Toyama, JP;

Takayuki Wakayama, Toyama, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/872 (2006.01); H01L 29/16 (2006.01); H01L 29/04 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/36 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/872 (2013.01); H01L 29/045 (2013.01); H01L 29/0619 (2013.01); H01L 29/0692 (2013.01); H01L 29/1608 (2013.01); H01L 29/6606 (2013.01); H01L 29/36 (2013.01); H01L 29/402 (2013.01);
Abstract

A semiconductor device according to an aspect of the present disclosure includes a semiconductor substrate having a first conductivity type and having a principal surface and a back surface, a silicon carbide semiconductor layer having the first conductivity type and disposed on the principal surface, barrier regions having a second conductivity type and disposed within the silicon carbide semiconductor layer, an edge termination region having the second conductivity type and disposed within the silicon carbide semiconductor layer, the edge termination region enclosing the barrier regions, a first electrode disposed on the silicon carbide semiconductor layer, and a second electrode disposed on the back surface, wherein each of the barrier regions has a polygonal boundary with the silicon carbide semiconductor layer, and each of sides of the polygonal boundary has an angle of 0° to 5° inclusive relative to <11-20> direction of crystal orientations of the semiconductor substrate.


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