The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 26, 2017
Filed:
Sep. 28, 2016
Applicant:
Applied Materials, Inc., Santa Clara, CA (US);
Inventors:
Peter Nunan, Monte Sereno, CA (US);
Xuena Zhang, San Jose, CA (US);
Assignee:
APPLIED MATERIALS, INC., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 21/324 (2006.01); H01L 21/266 (2006.01); H01L 21/268 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78696 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/02667 (2013.01); H01L 21/266 (2013.01); H01L 21/268 (2013.01); H01L 21/324 (2013.01); H01L 29/66765 (2013.01); H01L 29/78669 (2013.01); H01L 29/78678 (2013.01);
Abstract
The present disclosure generally relates to an improved large area substrate thin film transistor device, and method of fabrication thereof. More specifically, amorphous and LTPS transistors are formed by first forming an amorphous silicon layer, annealing the amorphous silicon layer to form polycrystalline silicon, depositing a masking layer over a first portion of the polycrystalline silicon layer, implanting a second portion of the polycrystalline silicon layer with an amorphizing species, and removing the masking layer.