The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2017

Filed:

Jun. 30, 2014
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Hefei Boe Optoelectronics Technology Co., Ltd., Hefei, Anhui, CN;

Inventors:

Haipeng Yang, Beijing, CN;

Yongjun Yoon, Beijing, CN;

Zhizhong Tu, Beijing, CN;

Jaikwang Kim, Beijing, CN;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 29/417 (2006.01); H01L 21/02 (2006.01); H01L 21/441 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 29/24 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); H01L 21/02565 (2013.01); H01L 21/441 (2013.01); H01L 21/76802 (2013.01); H01L 21/76832 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/53295 (2013.01); H01L 27/1259 (2013.01); H01L 29/24 (2013.01); H01L 29/4175 (2013.01); H01L 29/41733 (2013.01); H01L 29/42384 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78606 (2013.01); H01L 2924/0002 (2013.01);
Abstract

The present invention provides a thin film transistor and a manufacturing method thereof, an array substrate and a display device. The thin film transistor comprises a gate electrode, an active layer, an etch stop layer, a source electrode and a drain electrode. The etch stop layer is provided between the active layer and the source and drain electrodes, a first via hole and a second via hole are formed in the etch stop layer, the source electrode is connected with the active layer through the first via hole, the drain electrode is connected with the active layer through the second via hole, and the gate electrode is overlapped with a part of the first via hole and a part of the second via hole respectively and is overlapped with a portion between the first via hole and the second via hole.


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