The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2017

Filed:

Dec. 27, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Byoung Il Lee, Seoul, KR;

Kyung Jun Shin, Seoul, KR;

Dong Seog Eun, Seongnam-si, KR;

Ji Hye Kim, Anyang-si, KR;

Hyun Kook Lee, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8239 (2006.01); H01L 27/115 (2017.01); H01L 27/11582 (2017.01); H01L 27/11568 (2017.01); G11C 16/24 (2006.01); G11C 16/04 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 16/0466 (2013.01); G11C 16/24 (2013.01); H01L 27/11568 (2013.01); H01L 21/8239 (2013.01); H01L 21/823885 (2013.01);
Abstract

A semiconductor device includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating through the gate electrodes and the interlayer insulating layers, and a gate dielectric layer disposed on an external surface of the channel layer between the gate electrodes and the channel layer. In addition, the channel layer includes a first region extended in a direction perpendicular to a top surface of the substrate and a second region connected to the first region in a lower portion of the first region and including a plane inclined with respect to the top surface of the substrate.


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