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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9773802 B1

PDFFull Text
Date of Patent:
Sep. 26, 2017

Filed:

Jul. 13, 2016

Method of fabricating synapse memory device

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Xianyu Wenxu, Suwon-si, KR;

Inkyeong Yoo, Yongin-si, KR;

Hojung Kim, Suwon-si, KR;

Seong ho Cho, Gwacheon-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Gyeonggi-do, KR;

Attorney:

Harness, Dickey & Pierce P.L.C.

Primary Examiner:

Fei Fei Yeung Lopez

Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 27/1157 (2017.01); H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01); H01L 21/308 (2006.01); H01L 29/08 (2006.01); H01L 29/06 (2006.01); G11C 11/54 (2006.01); H01L 29/68 (2006.01); H01L 45/00 (2006.01); H01L 29/66 (2006.01); H01L 27/105 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1157 (2013.01); G11C 11/54 (2013.01); H01L 21/0217 (2013.01); H01L 21/02175 (2013.01); H01L 21/02183 (2013.01); H01L 21/02186 (2013.01); H01L 21/28282 (2013.01); H01L 21/308 (2013.01); H01L 21/76202 (2013.01); H01L 21/76224 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/685 (2013.01); H01L 45/00 (2013.01); H01L 27/1052 (2013.01); H01L 29/66833 (2013.01);
Abstract

Example embodiments relate to a method of fabricating a synapse memory device capable of being driven at a low voltage and realizing a multi-level memory. The synapse memory device includes a two-transistor structure in which a drain region of a first transistor including a memory layer and a first source region of a second transistor share a source-drain shared area. The synapse memory device is controlled by applying a voltage through the source-drain shared area. The memory layer includes a charge trap layer and a threshold switching layer, and may realize a non-volatile multi-level memory function.

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