The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2017

Filed:

Aug. 28, 2015
Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventors:

Guilei Wang, Beijing, CN;

Jinbiao Liu, Beijing, CN;

Jianfeng Gao, Beijing, CN;

Junfeng Li, Beijing, CN;

Chao Zhao, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 21/3215 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823828 (2013.01); H01L 29/66545 (2013.01); H01L 29/7845 (2013.01); H01L 21/28079 (2013.01); H01L 21/28088 (2013.01); H01L 21/3215 (2013.01); H01L 21/8238 (2013.01);
Abstract

There is provided a method for manufacturing a semiconductor device, including: providing a semiconductor substrate having a plurality of openings formed thereon by removing a sacrificial gate; filling the openings with a top metal layer having compressive stress; and performing amorphous doping with respect to the top metal layer in a PMOS device region. Thus, it is possible to effectively improve carrier mobility of an NMOS device, and also to reduce the compressive stress in the PMOS device region to ensure a desired performance of the PMOS device.


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