The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2017

Filed:

Jun. 05, 2015
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Manoj Kumar, Dhanbad, IN;

Tsung-Hsiung Lee, Taoyuan, TW;

Pei-Heng Hung, New Taipei, TW;

Chia-Hao Lee, New Taipei, TW;

Jui-Chun Chang, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/31 (2006.01); H01L 29/417 (2006.01); H01L 29/49 (2006.01); H01L 29/45 (2006.01); H01L 21/306 (2006.01); H01L 29/739 (2006.01); H01L 29/08 (2006.01); H01L 21/285 (2006.01); H01L 21/74 (2006.01);
U.S. Cl.
CPC ...
H01L 21/31 (2013.01); H01L 21/28518 (2013.01); H01L 21/30604 (2013.01); H01L 21/743 (2013.01); H01L 29/0834 (2013.01); H01L 29/41766 (2013.01); H01L 29/45 (2013.01); H01L 29/4975 (2013.01); H01L 29/7391 (2013.01);
Abstract

A semiconductor device is provided. The semiconductor device includes a substrate; an epitaxial layer disposed over the substrate; a gate electrode disposed over the epitaxial layer; a source region and a drain region disposed in the epitaxial layer at opposite sides of the gate electrode; a trench extending from a top surface of the epitaxial layer through the source region into the epitaxial layer, wherein the trench has a slanted side and a bottom surface; and a first conductive-type linking region having the first conductive type, wherein the first conductive-type linking region surrounds the slanted side of the trench and contacts the bottom surface of the trench, wherein the first conductive-type linking region electrically connects the source region and the substrate. The present disclosure also provides a method for manufacturing this semiconductor device.


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