The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 26, 2017
Filed:
Feb. 19, 2016
Applicant:
SK Hynix Inc., Icheon-si Gyeonggi-do, KR;
Inventor:
Ki Hun Kwon, Icheon-si, KR;
Assignee:
SK hynix Inc., Icheon-si, Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/12 (2006.01); G11C 5/06 (2006.01); G11C 7/10 (2006.01); G11C 8/10 (2006.01); G11C 29/26 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2006.01); G11C 5/02 (2006.01); G11C 29/18 (2006.01); G11C 29/46 (2006.01); G11C 8/12 (2006.01);
U.S. Cl.
CPC ...
G11C 29/1201 (2013.01); G11C 5/025 (2013.01); G11C 5/063 (2013.01); G11C 7/10 (2013.01); G11C 8/10 (2013.01); G11C 29/18 (2013.01); G11C 29/26 (2013.01); G11C 29/46 (2013.01); H01L 23/481 (2013.01); H01L 25/0657 (2013.01); G11C 8/12 (2013.01); G11C 2029/1206 (2013.01); G11C 2029/1802 (2013.01); H01L 2225/06541 (2013.01);
Abstract
A stack type semiconductor memory includes a plurality of stacked dies configured to transmit signals through a plurality of through electrodes. Any one die of the plurality of stacked dies is configured to provide preliminary test mode signals to other dies through the plurality of through electrodes, and the other dies are configured to generate test mode signals according to the preliminary test mode signals transmitted through the plurality of through electrodes.