The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 19, 2017
Filed:
Jul. 03, 2014
Applicant:
Lenovo Enterprise Solutions (Singapore) Pte. Ltd., Singapore, SG;
Inventors:
Larry G. Pymento, Cary, NC (US);
Tony C. Sass, Fuquay Varina, NC (US);
Paul A. Wormsbecher, Apex, NC (US);
Assignee:
Lenovo Enterprise Solutions (Singapore) Pte. Ltd., Singapore, SG;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 7/10 (2006.01); H05K 7/12 (2006.01); H05K 1/11 (2006.01); H05K 3/40 (2006.01); H05K 1/09 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
H05K 1/112 (2013.01); H05K 1/09 (2013.01); H05K 3/4015 (2013.01); H05K 3/3436 (2013.01); H05K 2201/10719 (2013.01); Y10T 29/49149 (2015.01); Y10T 29/49155 (2015.01); Y10T 29/49208 (2015.01);
Abstract
A land grid array (LGA) includes a grid array of metal pads plated directly onto a printed circuit board, and a discrete metal pad soldered to each of the plated metal pads in the grid array. Each discrete metal pad has an exposed contact surface after soldering, and a thickness of each discrete metal pad is selected as a function of location in the grid array so that the discrete pads provide a locus of exposed surfaces having greater flatness than the printed circuit board.