Jointly optimizing signal equalization and bit detection in a read channel

Abstract

An apparatus and associated methodology providing read channel circuitry having a signal equalizer that sends an equalized signal to a bit detector. The read channel circuitry is capable of sampling values of the equalized signal to identify a bit transition from among a predefined plurality of different bit transitions. The apparatus may have channel optimization (CO) logic that, based on the input signal and the sampling of the equalized signal, defines first values for a programmable parameter of the bit detector that substantially maximizes vector separations among vectors of waveform target samples corresponding to the predefined plurality of different bit transitions, while the CO logic also defines second values for a programmable parameter of the equalizer that substantially minimizes the mean squared separation of the equalized signal segment for each bit transition from the waveform target corresponding to that bit transition.